The present invention relates, in general, to semiconductor devices, and more particularly, to a novel field effect transistor (FET) that has a low "on" resistance.
In the past, the semiconductor industry has made field effect transistors, such as RF transistors, that have a backside or substrate source contact. The transistor's substrate source contact permits attaching the substrate to a grounded heat sink thereby providing a low thermal resistance. Such a low thermal resistance facilitates forming a high power dissipation semiconductor package. Additionally, the substrate source contact eliminates the need for a source wire bond thereby reducing the transistor's source inductance.
One disadvantage of these prior transistors is a high source to drain resistance, commonly referred to as the on resistance. For example, a transistor having a saturated output power of approximately two watts has a typical on resistance of one ohm or greater. The high on resistance results in undesirable power dissipation that limits the transistor's peak output power. In addition, these prior MOS transistors have a high gate to drain capacitance. For the example of the two watt transistor, the typical gate to drain capacitance is approximately 2.8 picofarads or greater. The high capacitance limits the transistor's high frequency stability thereby limiting the transistor's maximum operating frequency.
Accordingly, it is desirable to have a field effect transistor that has a low on resistance (less than approximately one ohm), and that has a low gate to drain capacitance (less than approximately 2.8 picofarads).